Semiconductor package structure and method of the same

ABSTRACT

The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second. portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of U.S. application Ser. No.14/795,331, filed Jul. 9, 2015.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package structure andassociated semiconductor packaging method.

DISCUSSION OF THE BACKGROUND

Within the electronics industry, vigorous development has focused onmulti-function and high-performance capabilities of electronic products.To meet the high-integration and miniaturization packaging requirementsof semiconductor package structures, a circuit board for carrying activeand passive components and wirings has evolved from a single-layer boardinto a multilayer board. In this way, an area of wire routing can beexpanded in a limited space on the circuit board by employing aninterlayer connection technique, which also complies with therequirements of high density integrated circuits.

A conventional semiconductor package structure includes a wire bondedsemiconductor die adhered to a front side of a substrate. Thesemiconductor die can be coupled to outside electrical components bydisposing solder balls on a back side of the substrate. Despite theobjective of achieving a high pin count, electrical efficiency is hardto improve at high frequencies due to a high impedance characteristiccaused by long wiring. In addition, fabrication of the conventionalsemiconductor package structure is highly complicated.

FIG. 1 is a cross-sectional view of a conventional semiconductor packagestructure. The semiconductor package structure 10 includes a substrate11, a die 12, a plurality of metal wires 13 and an encapsulationadhesive 14. The die 12 is fixed on a surface of the substrate 11 by anadhesive 15. The die 12 is further electrically connected to a pluralityof bonding pads 112 of the substrate 11 via the plurality of metal wires13. An insulating layer 111 of the substrate 11 includes a plurality ofconductive pillars 114, thus the plurality of bonding pads 112 can beelectrically connected to a plurality of pads 113 on a backside of thesubstrate 11 via the plurality of conductive pillars 114. Further, theplurality of pads 113 can be bonded to the solder balls (not shown inFIG. 1), thus forming a ball grid array (BOA) package. In order toprotect the die 12 and the plurality of metal wires 13 from beingdamaged, the die 12 and the plurality of metal wires 13 are capsulatedin the encapsulation adhesive 14.

The aforementioned semiconductor package structure requires not onlycomplicated operations such as die adhesion, wire bonding andencapsulating, but also a lead frame or circuit board to carry the die.Consequently, the cost of a package cannot be effectively reduced. Howto further improve the complex semiconductor packaging method has becomean urgent issue in this field.

SUMMARY

One of the objectives of the present invention is to disclosesemiconductor package structures and a method of the same, to solve theissue.

According to a first aspect of the present invention, a semiconductorpackage structure is disclosed. The semiconductor package structureincludes a substrate having a front side and a back side; a firstinsulating layer disposed on the front side of the substrate; and a diedisposed on the first insulating layer; wherein the die comprises afirst die pad and a second die pad, the first die pad is coupled to afirst portion of a metal layer, the second die pad is coupled to asecond portion of the metal layer, and the first portion of the metallayer and the second portion of the metal layer are spaced apart by asecond insulating layer.

According to a second aspect of the present invention, a semiconductorpackage structure is disclosed. The semiconductor package structureincludes a substrate; a first insulating layer disposed on thesubstrate; a first die disposed on the first insulating layer; and asecond die disposed on the first insulating layer; and wherein the firstdie comprises a first die pad and a second die pad, the second diecomprises a third die pad and a fourth die pad, the first die pad iscoupled to a first portion of a metal layer, the second die pad iscoupled to the third die pad via a second portion of the metal layer,the fourth die pad is coupled to a third portion of the metal layer, andthe first portion, the second portion and the third portion of the metallayer are spaced apart by a second insulating layer.

According to a third aspect of the present invention, a semiconductorpackaging method is disclosed. The semiconductor packaging methodincludes: providing a substrate having a front side and a back side;disposing a first insulating layer on the front side of the substrate;disposing a die on the first insulating layer, wherein the die comprisesa first die pad and a second die pad; disposing a second insulatinglayer on the first insulating layer, the die, the first die pad and thesecond die pad; removing a portion of the second insulating layer toform a first window and a second window, so as to expose the first diepad and the second die pad; disposing a first metal layer on the secondinsulating layer, the first window and the second window, and the firstmetal layer being coupled to the first die pad and the second die pad;disposing a third insulating layer on the first metal layer; removing aportion of the third insulating layer to form a third window and afourth window, so as to expose the first metal layer; disposing a secondmetal layer on the first metal layer in the third window and the fourthwindow; and removing the third insulating layer and a portion of thefirst metal layer, so as to uncouple the first die pad from the seconddie pad via the first metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a cross-sectional view of a conventional semiconductor packagestructure;

FIGS. 2-11 are cross-sectional views of a semiconductor packagestructure during a process of a semiconductor packaging method accordingto an embodiment of the disclosure;

FIG. 12 is a cross-sectional view of a semiconductor package structureaccording to an embodiment of the disclosure;

FIG. 13 is a cross-sectional view of a semiconductor package structureaccording to another embodiment of the disclosure; and

FIG. 14 is a cross-sectional view of a semiconductor package structureaccording to still another embodiment of the disclosure.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should be interpreted to mean “include, but notlimited to . . . ”. Also, the term “couple” is intended to mean eitheran indirect or direct electrical connection. Accordingly, if one deviceis electrically connected to another device, that connection may bethrough a direct electrical connection, or through an indirectelectrical connection via other devices and connections.

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should be interpreted to mean “include, but notlimited to . . . ”. Also, the term “couple” is intended to mean eitheran indirect or direct electrical connection. Accordingly, if one deviceis electrically connected to another device, that connection may bethrough a direct electrical connection, or through an indirectelectrical connection via other devices and connections.

FIGS. 2-11 are cross-sectional views of a semiconductor packagestructure during a process of a semiconductor packaging method accordingto an embodiment of the disclosure. Initially, a plurality of dies areobtained by sawing a wafer. At least one of the plurality of dies isarranged on a substrate 202 according to a predefined matrix and/or diesize after a pick and place process. The substrate 202 is an insulatingsubstrate. In order to facilitate illustration of the presentdisclosure, only a die 204 is depicted in the embodiment shown in FIGS.2-11. As shown in FIG. 2, a first insulating layer 206 and a protectionlayer 208 are adhered to a front side and a back side of the substrate202 respectively. It is preferred that the first insulating layer 206and the protection layer 208 are dry films including constituentsselected from at least one of polyimide, epoxy, benzocyclobutene resinand polymer. A curing process may be adopted to firmly bind the die 204on the surface of the first insulating layer 206. The protection layer208 may be employed to protect the substrate 202, in order to preventfragmentation of the substrate 202. However, this is not a limitation ofthe disclosure. In some embodiments, the protection layer 208 may beomitted. In this embodiment, the die 204 includes a first die pad 210and a second die pad 112. In some embodiments, the die 204 may includemore or less die pads.

Next, as shown in FIG. 3, a second insulating layer 302 is adhered tothe first insulating layer 206. The second insulating layer 302 coversthe die 204, the first die pad 210 and the second die pad 212. Where thesecond insulating layer 302 is a photosensitive dry film includingconstituents selected from at least one of polyimide, epoxy resin,benzocyclobutene resin and polymer. In FIG. 4, an expose developmentprocess is performed to transfer a predefined pattern to the secondinsulating layer 302 over the first die pad 210 and the second die pad212. A portion of the second insulating layer 302 is removed, andtherefore a first window 402 and a second window 404 are formed.Consequently, the first die pad 210 and the second die pad 212 can beexposed. In FIG. 5, a first metal layer 502 is deposited along a surfaceof the second insulating layer 302 and a profile of the first window 402and the second window 404. The first metal layer 502 is used a diffusionbarrier layer between the first die pad 210 and the second die pad 212and the subsequent metal layer in order to improve reliability ofelectrical characteristics, thus preventing copper atoms from drift ordiffusion once copper is included in the following metal layer. Thefirst metal layer 502 may include TiW, TiN, Ta, TaN, Ta—Si—N and WN. Thefirst metal layer 502 covers a surface of the third insulating layer, aprofile of the first window 402 and the second window 404, and theexposed first die pad 210 and the exposed second die pad 212 shown inFIG. 4.

As shown in FIG. 6, a third insulating layer 602 is deposit on the firstmetal layer 502. An exposure development process is performed totransfer a pattern to form a third window 702 and a fourth window 704 asillustrated in FIG. 7. Then an electroplating process can be performedto deposit a second metal layer 802 in the third window 702 and thefourth window 704 in FIG. 8 as bonding pads. In some embodiments, afterthe first metal layer 502 is finished and before the electroplatingprocess is started, a thin and continuous seed layer (not shown in FIG.8) can be formed in order to improve adhesion and facilitate growth ofcopper during the electroplating process. The second metal layer 802 maybe selected from at least one of Pd, Al, Cr, Ni, Ti, Au, Cu or Pt. Next,an insulating layer removing process can be used to strip out the thirdinsulating layer 602 and a portion of the first metal layer 502 notcovered by the second metal layer 802, as shown in FIG. 9. Then, afourth insulating layer 1002 is deposited to cover the second insulatinglayer 302, the first metal layer 502 and the second metal layer 802 asdepicted in FIG. 10. In FIG. 11, an exposure development process isperformed to transfer a pattern and form a structure of a fifth window1102 and a sixth window 1104, wherein the third insulating layer 602,the fourth insulating layer 1002 and the second insulating layer 302 mayinclude the same materials.

It can be understood by referring to FIG. 11 that the first die pad 210of the die 204 is coupled to a first portion (e.g. the left part of thesecond metal layer 802 of FIG. 11) of the second metal layer 802 via thefirst metal layer 502, and the second die pad 212 of the die 204 iscoupled to a second portion (e.g. the right part of the second metallayer 802 of FIG. 11) of the second metal layer 802 via the first metallayer 502. The first portion and the second portion are spaced apart byinsulating materials (e.g. the fourth insulating 1002 of FIG. 11). Inaddition, in this embodiment, it is optional to grind the substrate 202according to a required thickness. Further, as mentioned above, when thesubstrate 202 includes a plurality of dies, the substrate 202 may besawed based on the die number in order to obtain the singlesemiconductor package structure of FIG. 12. FIG. 12 is a cross-sectionalview of a semiconductor package structure according to an embodiment ofthe disclosure. The semiconductor package structure may be flipped overto couple the second metal layer 802 to external circuits by solder.Consequently, the semiconductor package structure can communicate withthe external circuits by electrical signals.

FIG. 13 is a cross-sectional view of a semiconductor package structureaccording to another embodiment of the disclosure. In some embodiments,a dip silver/copper operation may be performed upon two terminals of thesemiconductor of FIG. 12 as shown in FIG. 13, to form a first metalterminal 1302 and a second metal terminal 1304. The first metal terminal1302 and the second metal terminal 1304 are silver or copper, andfurther plated by metal materials such as nickel and tin by a barrelplating operation. Please note that in some embodiments, the first metalterminal 1302 and the second metal terminal 1304 may include other typesof metal, such as palladium, aluminum, chromium, nickel, titanium, goldor platinum. The semiconductor package structure of FIG. 13 may besoldered to the external circuits without being flipped over. In someembodiments, the semiconductor package structure of FIG. 13 may bedisposed on an external circuit board upright, upside down or on itsside, and communicates with the external circuit board by soldering.Thus, the facility can be greatly improved. In some embodiments, the die204 may include three or more die pads. Therefore, three or more dipsilver/copper metal terminals may be included in the semiconductorpackage structure.

FIG. 14 is a cross-sectional view of a semiconductor package structureaccording to still another embodiment of the disclosure. Thesemiconductor package structure of FIG. 14 includes a first die 1404 anda second die 1406 adhered to a first insulating layer 1408 on a frontside of the substrate 202. A protection 1410 is optionally adhered to aback side of the substrate 202. The first die 1404 includes a first diepad 1416 and a second die pad 1418; the second die 1406 includes a thirddie pad 1412 and a fourth die pad 1414. The semiconductor packagestructure of FIG. 14 further includes a second insulating layer 1420, afirst metal layer 1424, a second metal layer 1422, a third insulatinglayer 1428, a first metal terminal 1426 and a second metal terminal1430. The second die pad 1418 of the first die 1404 is coupled to thethird die pad 1412 of the second die 1406 via a second portion of thefirst metal layer 1424 and the second metal layer 1422. The first diepad 1416 of the first die 1404 is coupled to the first metal terminal1426 via a first portion of the first metal layer 1424 and the secondmetal layer 1422. The fourth die pad 1414 of the second die 1406 iscoupled to the second metal terminal 1430 via a third portion of thefirst metal layer 1424 and the second metal layer 1422.

The first die 1404 and the second die 1406 of the embodiment of FIG. 14may be capacitors to be packaged. By using the semiconductor packagestructure shown in FIG. 14, the first die 1404 and the second die 1406may be serially connected to perform a function different fromseparately adopting each single capacitor. In some embodiments, one ormore dies may be connected in serial/parallel by using the semiconductorpackage method mentioned above. The inner metal layers may be utilizedto connect some die pads of the dies to each other according to designrequirements, and coupling some die pads requires communication withexternal circuits to metal terminals at two sides of the substrate.

The dies mentioned in the disclosure are not limited to any specificcomponents. The dies mentioned in the disclosure may be any digitalcomponents, analog components, mix-signal components or active/passivecomponents, such as capacitors, resistors, inductors,transient-voltage-suppression (TVS) diode or computers.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor package structure, comprising: asubstrate; a first insulating layer disposed on the substrate; a firstdie disposed on the first insulating layer; and a second die disposed onthe first insulating layer; and wherein the first die comprises a firstdie pad and a second die pad, the second die comprises a third die padand a fourth die pad, the first die pad is coupled to a first portion ofa metal layer, the second die pad is coupled to the third die pad via asecond portion of the metal layer, the fourth die pad is coupled to athird portion of the metal layer, and the first portion, the secondportion and the third portion of the metal layer are spaced apart by asecond insulating layer.
 2. The semiconductor package structure of claim1, wherein at least a portion of each of the first portion and the thirdportion of the metal layer above two terminals of the substrate isexposed.
 3. The semiconductor package structure of claim 2, wherein thesemiconductor package structure comprises a first metal terminaldisposed on a terminal of the substrate and coupled to the first portionof the metal layer, and the semiconductor package structure comprises asecond metal terminal disposed on another terminal of the substrate andcoupled to the third portion of the metal layer.
 4. The semiconductorpackage structure of claim 3, wherein the first metal terminal and thesecond metal terminal are selected from at least one of silver andcopper.
 5. The semiconductor package structure of claim 1, wherein themetal layer is selected from at least one of palladium, aluminum,chromium, nickel, titanium, gold, copper and platinum.
 6. Thesemiconductor package structure of claim 1, wherein the first insulatinglayer and the second insulating layer are photosensitive dry filmscomprising constituents selected from at least one of polyimide, epoxyresin, benzocyclobutene resin and polymer.